參數(shù)資料
型號(hào)： PSD402A2-70U
英文描述： Field-Programmable Peripheral
中文描述： 現(xiàn)場(chǎng)可編程外圍
文件頁數(shù)： 71/123頁
文件大小： 657K
代理商： PSD402A2-70U
PSD4XX Famly
68
CLR
CLK
APD
COUNTER
APD CLK
PMMR1 - BIT 0
TO OTHER
CIRCUITS
MUX
APD
CLEAR
LOGIC
APD ENABLE
PMMR0 - BIT 2
ALE POLARITY
PMMR0 - BIT 1
ALE
RESET
APD CLK
CLKIN
CSI
SLEEP–ENABLE
PMMR1 - BIT 1
SLEEP
MODE
EPROM
SELECT
SRAM
SELECT
I/O
SELECT
POWER
DOWN
PD
Z
P
L
D
Figure 36. Power Management Unit
Figure 36a. Automatic Power Down Unit (APD) Flow Chart
APD DISABLED
NEED
APD CLK
YES
YES
NO
NO
RESET
SET APD CLK IN PMMR1 BIT 0
SET ALE PD POLARITY
IN PMMRO BIT 1
CSI = "1"
NEED
SLEEP
MODE
SET SLEEP MODE IN PMMR1 BIT 1
ALE IDLE and
15 APD CLOCK
ALE IDLE and
15 APD CLOCK
SET ENABLE APD IN PMMR0 BIT 2
SET PMMR0 BIT 0
SET ENABLE APD IN PMMR0 BIT 2
SET PMMR0 BIT 0
DISABLE CLOCKS
ZPLD ACLK, ZPLD RCLK, TMR ZPLD
DISABLE CLOCKS
ZPLD ACLK, ZPLD RCLK, TMR ZPLD
PSD IN POWER DOWN MODE
PSD IN SLEEP MODE
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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