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參數(shù)資料
| 型號： | PSD403A2-12J |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; A IRHE7230 with Standard Packaging |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 55/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD403A2-12J |
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PSD4XX Famly
52
9.3.9.1 Control Register
This register is used in both Standard MCU I/O Mode and Address Out modes. For setting
a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register.
Writing a “0” to the register is required for the Address Out mode. The register has a default
value of “0” after reset.
9.3.9.2 Drection Register
This register is used to control the direction of data flow in the I/O Ports. Writing a “1” to the
corresponding bit in the register configures the port to be an output port, and a “0” forces
the port to be an input port. The I/O configuration of the port pins can be determined by
reading the Direction Register. After reset, the pins are in input mode.
9.3.9.3 Open Drain
This register determines whether the output pin driver of Ports C or D is a CMOS driver or
an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects
an Open Drain driver.
9.3.9.4 PLD– I/ORegister
This is a read only status register. Reading a "1" indicates the corresponding pin is
configured as a PLD pin. A "0" indicates the pin is an I/O pin.
9.3.9.5 Data In Register
This register is used in the Standard MCU I/O Mode configuration to read the input pins.
9.3.9.6 Data Out Register
This register holds the output data in the Standard MCU I/O Mode. The contents of the
register can also be read.
9.3.9.7 Macrocell Out Register
This register enables the user to read the outputs of the GPLD macrocell
(PA, PB, and PE macrocells).
9.3.9.8 I/ORegister Address Ofset
The I/O Register can be accessed by the microcontroller during normal read/write bus
cycles. The address of a register is defined as:
CSIOP + register address offset
The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte
space. The register address offset lies within this 256 byte space. Tables 16 and 16a are
the address offset of the registers.
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD403A2-12JI | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 1000kRads |
| PSD403A2-12LI | Field-Programmable Peripheral |
| PSD403A2-12U | Field-Programmable Peripheral |
| PSD403A2-12UI | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-1 package; Similar to IRHN9150 with optional Total Dose Rating of 300kRads |
| PSD403A2-15J | Field-Programmable Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD403A2-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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