- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368150 > PSD403A2-12JI 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 1000kRads PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD403A2-12JI |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 1000kRads |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁數(shù)： | 5/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD403A2-12JI |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁
PSD4XX Famly
2
1.0
Introduction
(cont.)
The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be
individually configured to provide many functions, including the following:
MCU I/O
GPLD I/O
Latched address output (for MCUs with multiplexed data bus)
Data bus (for MCUs with non-multiplexed data bus).
The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a
multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the
ZPLDs, enabling the user to generate signals for external devices.
The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four
equal-sized blocks. Each block can occupy a different address location, allowing for
versatile address mapping. The access time of the EPROM includes the address latching
and DPLD decoding.
The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a
battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a
power failure. Therefore, you can place data in the SRAM that you want to keep after the
power is switched off. Power switchover to the battery automatically occurs when V
CC
drops
below V
stby
.
A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM for
microcontrollers with limited address space. The Page Register outputs are connected to
both ZPLDs and thus can also be used for external paging schemes.
The Power Management Unit (PMU) of the PSD4XX enables the user to control the
power consumption on selected functional blocks, based on system requirements.
For microcontrollers that do not generate a chip select input for the PSD, the Automatic
Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down
Mode or Sleep Mode, based on the inactivity of ALE (or AS).
Implementing your design has never been easier than with PSDsoft—
ST
’s software
development suite. Using PSDsoft, you can do the following:
Configure your PSD4XX to work with virtually any microcontroller
Specify what you want implemented in the programmable logic using a design file
Simulate your design
Download your design to the part using a programmer.
2.0
Key Features
J
Single-chip programmable peripheral for microcontroller-based applications
J
256K to 1 Mbit of UV EPROM with the following features:
Configurable as 32, 64, or 128 K x 8; or as 16, 32, or 64 K x 16
Divided into four equally-sized mappable blocks for optimized address mapping
As fast as 70 ns access time, which includes address decoding
Built-in Zero-power technology
J
16 Kbit SRAM is configurable as 2K x 8 or 1K x 16. The access time can be as
quick as 70 ns, including address decoding. The contents of the SRAM can be
battery-backed by connecting a battery to the Vstby pin. The SRAM also has built-in
Zero-power technology.
J
40 I/O pins (divided into five 8-bit ports) that can be individually configured for:
Standard MCU I/O
PLD/macrocell I/O
Latched address output
High-order address inputs
Special function I/O
Open-drain output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD403A2-12LI | Field-Programmable Peripheral |
| PSD403A2-12U | Field-Programmable Peripheral |
| PSD403A2-12UI | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-1 package; Similar to IRHN9150 with optional Total Dose Rating of 300kRads |
| PSD403A2-15J | Field-Programmable Peripheral |
| PSD403A2-15JI | Field-Programmable Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD403A2-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。