參數(shù)資料
型號: PSD403A2-C-70L
廠商: 意法半導體
英文描述: TVS BI-DIR 12V 600W DO-15
中文描述: 低成本現(xiàn)場可編程微控制器外圍設備
文件頁數(shù): 95/123頁
文件大?。?/td> 657K
代理商: PSD403A2-C-70L
PSD4XX Famly
92
-20
-25
EPROM_CMiser
ON
Symbol
Parameter
Conditions
Min Max Min Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
30
30
ns
Address Setup Time
(Note 1)
12
15
ns
Address Hold Time
(Note 1)
12
17
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
35
50
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
40
60
ns
WR Data Setup Time
(Note 3)
25
35
ns
WR Data Hold Time
(Note 3)
5
10
ns
WR Pulse Width
(Note 3)
30
30
ns
t
WHAX
Trailing Edge of WR to Address
Invalid
(Note 3)
0
0
ns
t
WHPV
Trailing Edge of WR to Port
Output Valid
(Note 3)
50
60
ns
In 16-Bit Data Bus
Mode (Note 2)
40
60
ns
Address Input Valid to
Address Output Delay
t
AVPV
In 8-Bit Data Bus
Mode (Note 2)
50
60
ns
Write Timng
(3.0 V ± 10%)
Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
NOTES:
1. Any input used to select an internal PSD4XX function.
2. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.
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