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參數(shù)資料
| 型號： | PSD403A2 |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 300kRads |
| 中文描述： | PSD4XX/ZPSD4XX家庭領(lǐng)域，可編程微控制器外設(shè) |
| 文件頁數(shù)： | 54/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD403A2 |
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PSD4XX Famly
51
Register Name
Port
Write/Read
Control Register
A,B,C,D,E
Write/Read
Direction Register
A,B,C,D,E
Write/Read
Open Drain Register
C,D
Write/Read
PLD – I/O Register
A,B,E
Read
Table 13. Port Configuration Registers (PCR)
Register Name
Port
Read/Write
Data In Register
A,B,C,D,E
Read
Data Out Register
A,B,C,D,E
Write/Read
Macrocell Out Register
A,B,E
Read
Table 14. Port Data Registers (PDR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
Table 15.
Data In Register – Port A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
= 0
= 0
= 0
= 0
= 0
= 1
= 1
= 1
Drection Register – Port A
(Example: Pins PA0 – PA2 as Output, PA3 – PA7 as Input)
9.3.9 Port Registers
There are two sets of registers per I/O port: the Port Configuration Registers (PCR) which
consist of four 8-bit registers; and the Port Data Registers (PDR) which include three 8-bit
registers. The PCR is used for setting up the port configuration, while the PDR enables the
microcontroller to write or read port data or status bits. Tables 13 and 14 show the names
and the registers and the ports to which they belong.
All the registers in the PCR and PDR are 8-bits wide and each bit is associated with a
pin in the I/O port. In Table 15, the LSB of the Data In Register of Port A is connected to
pin PA0, and the MSB is connected to PA7. This pin configuration also applies to other
registers and ports. For example, in the Direction Register of Port A, writing a hex value of
07 to the register configures pins PA0 – PA2 as output pins, while PA3 – PA7 remain as
input pins.
Registers can be accessed by the microcontroller during normal read/write bus cycles.
The I/O address offset of the registers are listed in the System Configuration section.
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD403A2-12J | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; A IRHE7230 with Standard Packaging |
| PSD403A2-12JI | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 1000kRads |
| PSD403A2-12LI | Field-Programmable Peripheral |
| PSD403A2-12U | Field-Programmable Peripheral |
| PSD403A2-12UI | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-1 package; Similar to IRHN9150 with optional Total Dose Rating of 300kRads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD403A2-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD403A2-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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