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參數(shù)資料
| 型號： | PSD411A1-15UI |
| 英文描述： | 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; JANS Certified Part Number |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 33/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD411A1-15UI |
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PSD4XX Famly
30
The PSD4XX
Architecture
(cont.)
9.1.2.4 Port B Macrocell Structure
Figure 16 shows the PB Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and
MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes
directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin
except it is user configurable.
The circuit of a PB Macrocell is shown in Figure 17. There are 10 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output,
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop.
J
Combinatorial Output
Select output from OR gate.
J
GPLD Input
Use Port B pin as dedicated input.
J
GPLD Output
Use Port B pin as dedicated output.
J
GPLD I/O
Use Port B pin as bidirectional pin.
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback
from the combinatorial output, to possibly expand the number of product terms
available to another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not
connected to a Port B pin, Port B can be configured to perform other user
defined I/O functions.
Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and
clock input. The signals are defined as follow:
J
PRESET
Active only if defined by a product term (PBx.PR)
J
CLEAR
Two selectable inputs: Reset input or user defined product term (PBx .RE)
J
CLK
Two selectable inputs – CLKIN input or user defined product term (PBx.CLK).
The macrocell is operated in Synchronous Mode if the clock input is
CLKIN, and is in Asynchronous Mode if the clock is a product-term clock
defined by the user.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD411A1-20J | 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; JANS Certified device. Equivalent to IR Part Number IRHNA57264SE |
| PSD411A1-20JI | -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597Z60 with Standard Packaging |
| PSD411A1-20LI | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package; Similar to IRHYB67230CM with optional Total Dose Rating of 300kRads |
| PSD411A1-20LM | 200V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA Tabless package; A IRHMK57260SE with Standard Packaging |
| PSD411A1-20U | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-205AF package; A IRHF9230 with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD411A1-20J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-20JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-20LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-20LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-20U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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