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| 型號(hào)： | PSD411A1-20LM |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA Tabless package; A IRHMK57260SE with Standard Packaging |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 46/123頁(yè) |
| 文件大?。?/td> | 657K |
| 代理商： | PSD411A1-20LM |
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9.2.5 Optional Features
The PSD4XX provides two optional features to add flexibility to the Bus Interface:
1. Address In
Port A can be configured as high order address (A16-A23) inputs to the ZPLD for
EPROM or other decoding. Inputs are latched by ALE/AS if Multiplexed Bus is selected.
Other Ports can be configured as address input ports for the ZPLD. These inputs should
not be used for EPROM decoding and are not latched internally.
2. Address Out
For multiplexed bus only. Latched address lines A0-A15 are available on
Port A, B, C or D.
Details on the optional features are described in the I/O Port section.
9.2.6 Bus Interface Examples
The next four figures show the PSD4XX interfacing with some popular microcontrollers.
The examples show only the basic bus connections; some of the pin names on the
PSD4XX parts change to reflect the actual pin functions.
Figure 23 shows the interface to the 80C31. The 80C31 has a 16 bit address bus and an
8-bit data bus. The lower address byte is multiplexed with the data bus. The RD and WR
signals are used for accessing the data memory (SRAM) and the PSEN signal is for
reading program memory (EPROM). The ALE signal is active high and is used to latch the
address internally. Port C provides latched address outputs A[7:0]. Ports A, B, D, and E
(PE2-PE7) can be configured to perform other functions. The RSTOUT reset to the 80C31
is generated by the ZPLD from the RESET input. This configuration eliminates any reset
race condition between the 80C31 and the PSD4XX.
Figure 24 shows the 68HC11 interface, which is similar to the 80C31 except the PSD4XX
generates internal RD and WR from the 68HC11’s E and R/W signals.
In Figure 25, the Intel 80C196 microcontroller is interfaced to the PSD4XX. The 80C196
has a multiplexed 16-bit address and data bus. The BHE signal is used for data byte
selection. Ports C and D are used as output ports for latched address A[15:0]. Pins PE6
and PE7 can be programmed as ZPLD outputs to provide the READY and BUSWIDTH
control signals to the 80C196.
Figure 26 shows Motorola’s MC68331 interfacing to the PSD4XX. The MC68331 has a
16-bit data bus and a 24-bit address bus. D15 – D8 from the MC68331 are connected to
Port D, and D7 – D0 are connected to Port C.
PSD4XX Famly
43
The PSD4XX
Architecture
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
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| PSD411A1-20U | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Peripheral |
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| PSD411A1-70J | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-70U | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Peripheral |
| PSD411A1-90J | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Peripheral |
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