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參數(shù)資料
| 型號： | PSD412A2-12UI |
| 英文描述： | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-205AF package; Similar to IRHF7110 with optional Total Dose Rating of 500kRads |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 72/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD412A2-12UI |
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PSD4XX Famly
69
APDENBit
ALE Power
Down Polarity
X
ALE Status
APDCounter
0
X
Not Counting
1
X
Pulsing
Not Counting
Counting (Activates Standby
Mode After 15 Clocks)
Counting (Activates Standby
Mode After 15 Clocks)
1
1
1
1
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR CLK
ZPLD
RCLK
ZPLD
ACLK
ZPLD
TURBO
APD
ENABLE
ALE PD
Polarity
*
CMISER
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = ON
1 = ON
1 = HIGH
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
Sleep
Mode
APD CLK
1 = ON
1 = CLKIN
PMMR1
Table 18. Power Management Mode Registers (PMMR0, PMMR1)
Table 19. APDCounter Operation
Bit 0
*
= Should be set to High (1) to operate the APD.
Bit 1
0 = ALE Power Down (PD) Polarity Low.
1 = ALE Power Down (PD) Polarity High.
Bit 2
0 = Automatic Power Down (APD) Disable.
1 = Automatic Power Down (APD) Enable.
Bit 3
0 = EPROM/SRAM CMiser is OFF.
1 = EPROM/SRAM CMiser is ON.
Bit 4
0 = ZPLD Turbo is ON. ZPLD is always ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
Bit 5
0 = ZPLD Clock Input into the Array from the CLKIN pin input is connected.
Every Clock change will Power Up the ZPLD when Turbo bit is OFF.
1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected.
Bit 6
0 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is connected.
1 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is disconnected.
Bit 7
*
= In the PSD4XX should be set to High (1)
Bit 0
0 = Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
function input.
1 = Automatic Power Down Unit Clock is connected to the PSD Clock
input (CLKIN).
0 = Sleep Mode Disabled.
1 = Sleep Mode Enabled.
Bit 2–7
0 = Reserved for future use, should be set to zero.
Bit 1
The PSD4XX
Architecture
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD412A2-15J | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-205AF package; Similar to IRHF7110 with optional Total Dose Rating of 1000kRads |
| PSD412A2-15JI | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low Ohmic TO-254AA package. Also available in 300, 600 and 1000kRad.; Similar to IRHMS57160 with optional Total Dose Rating of 500kRads |
| PSD412A2-15LI | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low Ohmic TO-254AA package. Also available in 300, 600 and 1000kRad.; Similar to IRHMS57160 with optional Total Dose Rating of 1000kRads |
| PSD412A2-15U | Field-Programmable Peripheral |
| PSD412A2-15UI | Field-Programmable Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD412A2-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A2-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A2-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A2-15U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A2-15UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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