- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368160 > PSD4135F2-A-12U (意法半導體) Flash In-System-Programmable Peripherals for 16-Bit MCUs PDF資料下載
參數(shù)資料
| 型號： | PSD4135F2-A-12U |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設的16位微控制器 |
| 文件頁數(shù)： | 73/93頁 |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135F2-A-12U |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
PSD4000 Series
Preliminary Information
70
-70
-90
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
15
20
Address Setup Time
(Note 1)
4
6
ns
Address Hold Time
(Note 1)
7
8
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
8
15
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
WR Data Setup Time
(Note 3)
25
35
ns
WR Data Hold Time
(Note 3)
4
5
ns
WR Pulse Width
(Note 3)
28
35
ns
t
WHAX1
Trailing Edge of WR to Address
Invalid
(Note 3)
6
8
ns
t
WHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Note 3 and 4)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
ns
Write Timing
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD4000 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
t
WHAX2
is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
2.
3.
4.
Microcontroller Interface – PSD4000 AC/DC Parameters
(5V ±10% Versions)
-70
-90
Slew
Rate
(Note 1)
TURBO
OFF
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PD
PLD Input Pin/Feedback to
PLD Combinatorial Output
20
25
Add 12
Sub 2
ns
t
ARD
PLD Array Delay
11
16
ns
PLD Combinatorial Timing
(5 V ± 10%)
NOTE:
1. Fast Slew Rate output available on Port C and F.
相關PDF資料 |
PDF描述 |
|---|---|
| PSD4135F2-A-12UI | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 1000pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
| PSD4135F2-A-15B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15J | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 1000pF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
| PSD4135F2-A-15JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15M | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135F2-A-12UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2-A-15JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復。