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參數(shù)資料
| 型號(hào)： | PSD4135F2V-A-20B81 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 2200pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1210; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.126" x 0.098"; Container: Bulk; Features: Unmarked |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 56/93頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | PSD4135F2V-A-20B81 |
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Preliminary Information
PSD4000 Series
53
The
PSD4000
Functional
Blocks
(cont.)
9.4.6 Port D – Functionality and Structure
Port D has four I/O pins. See Figure 22. Port D can be configured to program one or more
of the following functions:
J
MCU I/O Mode
J
PLD Input
–
direct input to PLD
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
J
PD0
–
ALE, as address strobe input
J
PD1
–
CLKIN, as clock input to the PLD and APD counter
J
PD2
–
CSI, as active low chip select input. A high input will disable the
Flash/SRAM and CSIOP.
J
PD3
–
WRH, as active low Write Enable (high byte) input or as DBE input from
68HC912
9.4.7 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions (see Figure 23):
J
MCU I/O Mode
J
In-System Programming
–
JTAG port can be enabled for programming/erase of the
PSD4000 device. (See Section 9.6 for more information on JTAG programming.)
Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O
functions.
J
Open Drain
–
Port E pins can be configured in Open Drain Mode
J
Battery Backup features
–
PE6 can be configured as a Battery Input (Vstby) pin.
PE7 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
J
Latched Address Output
–
Provided latched address (A7-0) output
I
DATA OUT
REG.
D
Q
D
Q
WR
WR
READ MUX
P
D
B
PLD INPUT
DIR REG.
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
Figure 22. Port D Structure
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4135F2V-A-20B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20J | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20M | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135F2V-A-20B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135F2V-A-20MI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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