
PSD4000 Series
Preliminary Information
54
The
PSD4000
Functional
Blocks
(cont.)
I
DATA OUT
REG.
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
ALE
READ MUX
P
D
B
CONTROL REG.
DIR REG.
PLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
CONFIGURATION
BIT
Figure 23. Ports E, F and G Structure
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
PLD Input
–
as direct input ot the PLD array.
J
Address In
–
additional high address inputs. Direct input to the PLD array.
J
Latched Address Out
–
Provide latched address out per Table 29.
J
Slew Rate
–
pins can be set up for fast slew rate.
J
Data Port
–
connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
J
MCU Reset Mode
–
for 16-bit Motorola 683XX and HC16 microcontrollers.
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
Latched Address Out
–
provide latched address out per Table 29.
J
Open Drain
–
pins can be configured in Open Drain Mode
J
Data Port
–
connected to D[15:8] when Port G is configured as Data Port for a
non-multiplexed bus.
J
MCU Reset Mode
–
for 16-bit Motorola 683XX and HC16 microcontrollers