參數(shù)資料
型號(hào)： PSD4135G1-A-20UI
廠商： 意法半導(dǎo)體
英文描述： Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 3300pF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-2%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1812; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.126"; Container: Bulk; Features: Unmarked
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù)： 33/93頁(yè)
文件大?。?/td> 503K
代理商： PSD4135G1-A-20UI
PSD4000 Series
Preliminary Information
30
The
PSD4000
Functional
Blocks
(cont.)
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Memory_ID0 Register
Main Flash Size
(Bit)
none
256K
512K
1M
2M
4M
8M
F_size3
0
0
0
0
0
0
0
F_size2
0
0
0
0
1
1
1
F_size1
0
0
1
1
0
0
1
F_size0
0
1
0
1
0
1
0
Bit Definition
SRAM Size
(Bit)
none
16K
32K
64K
S_size3
0
0
0
0
S_size2
0
0
0
0
S_size1
0
0
1
1
S_size0
0
1
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
Memory_ID1 Register
*
Not used bit should be set to zero.
Boot Block Size
(Bit)
none
128K
256K
512K
B_size3
0
0
0
0
B_size2
0
0
0
0
B_size1
0
0
1
1
B_size0
0
1
0
1
Bit Definition
B_type1
0
0
B_type0
0
1
Boot Block Type
Flash
EEPROM
相關(guān)PDF資料
PDF描述
PSD4135G1-A-70B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70J Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70MI Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 3300pF; Working Voltage (Vdc)[max]: 200V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1812; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.177" x 0.126"; Container: Bulk; Features: Unmarked
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4135G1-A-70B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G1-A-70M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs
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