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    參數(shù)資料
    型號(hào)： PSD4135G1V-15UI
    廠商： 意法半導(dǎo)體
    英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
    文件頁(yè)數(shù)： 70/93頁(yè)
    文件大小： 503K
    代理商： PSD4135G1V-15UI
    Preliminary Information
    PSD4000 Series
    67
    NOTE:
    1. Reset input has hysteresis. V
    IL1
    is valid at or below .2V
    CC
    –.1. V
    IH1
    is valid at or above .8V
    CC
    .
    2. CSI deselected or internal Power Down mode is active.
    3. PLD is in non-turbo mode and none of the inputs are switching
    4. Refer to Figure 32 for PLD current calculation.
    5. I
    O
    = 0 mA
    Symbol
    Parameter
    Conditions
    Min
    Typ
    Max
    Unit
    V
    CC
    V
    IH
    V
    IL
    V
    IH1
    V
    IL1
    V
    HYS
    V
    LKO
    Supply Voltage
    All Speeds
    4.5
    5
    5.5
    V
    High Level Input Voltage
    4.5 V < V
    CC
    < 5.5 V
    4.5 V < V
    CC
    < 5.5 V
    (Note 1)
    2
    V
    CC
    +.5
    0.8
    V
    Low Level Input Voltage
    –.5
    V
    Reset High Level Input Voltage
    .8 V
    CC
    –.5
    V
    CC
    +.5
    .2 V
    CC
    –.1
    V
    Reset Low Level Input Voltage
    (Note 1)
    V
    Reset Pin Hysteresis
    0.3
    V
    V
    CC
    Min for Flash Erase and Program
    2.5
    4.2
    V
    V
    OL
    Output Low Voltage
    I
    OL
    = 20 μA, V
    CC
    = 4.5 V
    0.01
    0.1
    V
    I
    OL
    = 8 mA, V
    CC
    = 4.5 V
    I
    OH
    = –20 μA, V
    CC
    = 4.5 V
    0.25
    0.45
    V
    V
    OH
    Output High Voltage Except V
    STBY
    On
    4.4
    4.49
    V
    I
    OH
    = –2 mA, V
    CC
    = 4.5 V
    I
    OH1
    = –1 μA
    2.4
    3.9
    V
    V
    OH1
    V
    SBY
    I
    SBY
    I
    IDLE
    V
    DF
    Output High Voltage V
    STBY
    On
    SRAM Standby Voltage
    V
    SBY
    – 0.8
    2.0
    V
    V
    CC
    1
    V
    SRAM Standby Current (V
    STBY
    Pin)
    Idle Current (V
    STBY
    Pin)
    SRAM Data Retention Voltage
    V
    CC
    = 0 V
    V
    CC
    > V
    SBY
    Only on V
    STBY
    0.5
    μA
    –0.1
    0.1
    μA
    2
    V
    I
    SB
    Standby Supply Current for Power
    Down Mode
    CSI > V
    CC
    –0.3 V
    (Notes 2, 3 and 5)
    100
    200
    μA
    I
    LI
    I
    LO
    Input Leakage Current
    V
    SS
    < V
    IN
    < V
    CC
    0.45 < V
    IN
    < V
    CC
    –1
    ±.1
    1
    μA
    Output Leakage Current
    –10
    ±5
    10
    μA
    I
    O
    Output Current
    Refer to I
    OL
    and I
    OH
    in
    the V
    OL
    and V
    OH
    row
    PLD_TURBO = OFF,
    f = 0 MHz (Note 3)
    0
    mA
    PLD Only
    PLD_TURBO = ON,
    f = 0 MHz
    400
    700
    μA/PT
    I
    CC
    (DC)
    (Note 5)
    Operating Supply
    Current
    During Flash Write/Erase
    Only
    Flash
    15
    30
    mA
    Read Only, f = 0 MHz
    0
    0
    mA
    SRAM
    f = 0 MHz
    0
    0
    mA
    PLD AC Base
    Fig. 27
    (Note 4)
    I
    CC
    (AC)
    (Note 5)
    FLASH AC Adder
    2.5
    3.5
    mA/MHz
    SRAM AC Adder
    1.5
    3.0
    mA/MHz
    PSD4000 DC Characteristics
    (5 V ± 10% Versions)
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