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        參數(shù)資料
        型號(hào): PSD4135G1V-70M
        廠商: 意法半導(dǎo)體
        英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
        中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
        文件頁數(shù): 20/93頁
        文件大小: 503K
        代理商: PSD4135G1V-70M
        Preliminary Information
        PSD4000 Series
        17
        FS0-7
        or
        CSBOOT0-3
        Instruction
        (Note 14)
        Cycle 1 Cycle 2 Cycle 3
        Cycle 4
        Cycle5
        Cycle 6
        Cycle 7
        Read (Note 5)
        1
        “Read”
        RA RD
        Read Main Flash ID
        (Note 6)
        1
        AAh
        55h
        90h
        “Read”
        ID
        @XX02h
        @XAAAh @X554h @XAAAh
        Read Sector Protection
        (Notes 6,8,13)
        1
        AAh
        55h
        90h
        “Read”
        @XAAAh @X554h @XAAAh 00h or 01h
        @XX04h
        Program a Flash Word
        1
        AAh
        55h
        A0h
        PD@PA
        @XAAAh @X554h @XAAAh
        Erase One Flash Sector
        1
        AAh
        55h
        80h
        AAh
        55h
        30h
        @SA
        30h
        @XAAAh @X554h @XAAAh
        @XAAAh
        @X554h
        @next SA
        (Note 7)
        Erase Flash Block
        (Bulk Erase)
        1
        AAh
        55h
        80h
        AAh
        55h
        10h
        @XAAAh @X554h @XAAAh
        @XAAAh
        @X554h
        @XAAAh
        Suspend Sector Erase
        (Note 11)
        1
        B0h
        @xxxh
        Resume Sector Erase
        (Note 12)
        1
        30h
        @xxxh
        Reset (Note 6)
        1
        F0 @ any
        address
        Unlock Bypass
        1
        AAh
        55h
        20h
        @XAAAh @X554h @XAAAh
        Unlock Bypass Program
        (Note 9)
        1
        A0h
        PD@PA
        @XXXXh
        Unlock Bypass Reset
        (Note 10)
        1
        90h
        00h
        @XXXXh @XXXXh
        Table 8. Instructions
        X
        RA = Address of the memory location to be read.
        RD = Data read from location RA during read operation.
        PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
        (CNTL0) pulse. PA is an even address for PSD in word programming mode.
        PD = Data (word) to be programmed at location PA. Data is latched on the rising edge of WR# (CNTL0) pulse.
        SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
        erased must be active (high).
        = Don’t Care. “xxxh” address in the above table must be an even address.
        NOTES:
        1.
        All bus cycles are write bus cycle except the ones with the “read” label.
        2.
        All values are in hexadecimal.
        3.
        FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
        4.
        Only Address bits A11-A0 are used in Instruction decoding.
        5.
        No unlock or command cycles required when device is in read mode.
        6.
        The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
        or if DQ5 (DQ13) goes high.
        7.
        Additional sectors to be erased must be entered within 80μs.
        8.
        The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
        select is active and (A1 = 1, A0 = 0).
        9.
        The Unlock Bypass command is required prior to the Unlock Bypass Program command.
        10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
        Unlock Bypass mode.
        11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
        Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
        erase operation.
        12. The Erase Resume command is valid only during the Erase Suspend mode.
        13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
        instruction is intended. The MCU must fetch, for example, codes from the Secondary Flash memory when
        reading the Sector Protection Status of the main Flash.
        14. All write bus cycles in an instruction are byte write to even address (XA4Ah or X554h). Flash Programming
        bys cycle is writing a word to even address.
        The
        PSD4000
        Functional
        Blocks
        (cont.)
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