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    參數(shù)資料
    型號(hào): PSD4135G1V-70U
    廠商: 意法半導(dǎo)體
    英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
    文件頁(yè)數(shù): 21/93頁(yè)
    文件大?。?/td> 503K
    代理商: PSD4135G1V-70U
    PSD4000 Series
    Preliminary Information
    18
    The
    PSD4000
    Functional
    Blocks
    (cont.)
    9.1.1.4 Power-Up Condition
    The PSD4000 internal logic is reset upon power-up to the read array mode. The FSi and
    CSBOOTi select signals, along with the write strobe signal, must be in the false state
    during power-up for maximum security of the data contents and to remove the possibility of
    data being written on the first edge of a write strobe signal. Any write cycle initiation is
    locked when V
    CC
    is below VLKO.
    9.1.1.5 Read
    Under typical conditions, the microcontroller may read the Flash, or secondary Flash
    memories using read operations just as it would a ROM or RAM device. Alternately, the
    microcontoller may use read operations to obtain status information about a program or
    erase operation in progress. Lastly, the microcontroller may use instructions to read
    special data from these memories. The following sections describe these read functions.
    9.1.1.5.1 Read the Contents of Memory
    Main Flash and secodary Flash memories are placed in the read array mode after
    power-up, chip reset, or a Reset Flash instruction (see Table 8). The microcontroller can
    read the memory contents of main Flash or secondary Flash by using read operations any
    time the read operation is not part of an instruction sequence.
    9.1.1.5.2 Read the Main Flash Memory Identifier
    The main Flash memory identifier is read with an instruction composed of 4 operations:
    3 specific write operations and a read operation (see Table 8). The PSD4000 main Flash
    memory ID is E8h. The Secondary Flash does not support this instruction.
    9.1.1.5.3 Read the Flash Memory Sector Protection Status
    The Flash memory sector protection status is read with an instruction composed of 4
    operations: 3 specific write operations and a read operation (see Table 8). The read
    operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
    protected.
    The sector protection status for all NVM blocks (main Flash or secondary Flash) can also
    be read by the microcontroller accessing the Flash Protection and Flash Boot Protection
    registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
    9.1.1.5.4 Read the Erase/Program Status Bits
    The PSD4000 provides several status bits to be used by the microcontroller to confirm
    the completion of an erase or programming instruction of Flash memory. These status bits
    minimize the time that the microcontroller spends performing these tasks and are defined
    in Table 9. The status byte resides in even location and can be read as many times as
    needed. Please note DQ15-8 is even byte for Motorola MCUs with 16 bit data bus.
    Table 9. Status Bits
    FSi/
    CSBOOTi
    DQ7
    DQ6
    DQ5
    DQ4
    DQ3
    Erase
    Time-
    out
    DQ2
    DQ1
    DQ0
    Data
    Polling
    Toggle
    Flag
    Error
    Flag
    Flash
    V
    IH
    X
    X
    X
    X
    NOTES:
    1. X = Not guaranteed value, can be read either 1 or 0.
    2. DQ15-DQ0 represent the Data Bus bits, D15-D0.
    3. FSi/CSBOOTi are active high.
    For Flash memory, the microcontroller can perform a read operation to obtain these status
    bits while an erase or program instruction is being executed by the embedded algorithm.
    See section 9.1.1.6 for details.
    FSi/
    CSBOOTi
    DQ15
    DQ14
    DQ13
    DQ12
    DQ11
    Erase
    Time-
    out
    DQ10
    DQ9
    DQ8
    Data
    Polling
    Toggle
    Flag
    Error
    Flag
    Flash
    V
    IH
    X
    X
    X
    X
    Table 9A. Status Bits for Motorola
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