參數資料
型號： PSD413A1-20UI
英文描述： -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-204AA package; A IRH9130 with Standard Packaging
中文描述： 現場可編程外圍
文件頁數： 55/123頁
文件大小： 657K
代理商： PSD413A1-20UI
PSD4XX Famly
52
9.3.9.1 Control Register
This register is used in both Standard MCU I/O Mode and Address Out modes. For setting
a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register.
Writing a “0” to the register is required for the Address Out mode. The register has a default
value of “0” after reset.
9.3.9.2 Drection Register
This register is used to control the direction of data flow in the I/O Ports. Writing a “1” to the
corresponding bit in the register configures the port to be an output port, and a “0” forces
the port to be an input port. The I/O configuration of the port pins can be determined by
reading the Direction Register. After reset, the pins are in input mode.
9.3.9.3 Open Drain
This register determines whether the output pin driver of Ports C or D is a CMOS driver or
an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects
an Open Drain driver.
9.3.9.4 PLD– I/ORegister
This is a read only status register. Reading a "1" indicates the corresponding pin is
configured as a PLD pin. A "0" indicates the pin is an I/O pin.
9.3.9.5 Data In Register
This register is used in the Standard MCU I/O Mode configuration to read the input pins.
9.3.9.6 Data Out Register
This register holds the output data in the Standard MCU I/O Mode. The contents of the
register can also be read.
9.3.9.7 Macrocell Out Register
This register enables the user to read the outputs of the GPLD macrocell
(PA, PB, and PE macrocells).
9.3.9.8 I/ORegister Address Ofset
The I/O Register can be accessed by the microcontroller during normal read/write bus
cycles. The address of a register is defined as:
CSIOP + register address offset
The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte
space. The register address offset lies within this 256 byte space. Tables 16 and 16a are
the address offset of the registers.
The PSD4XX
Architecture
(cont.)
相關PDF資料
PDF描述
PSD413A1-70J Field-Programmable Peripheral
PSD413A1-70U 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-257AA Low-Ohmic Tabless package; A IRHYB597034CM with Standard Packaging
PSD413A1-90J 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ57230 with optional Total Dose Rating of 500kRads
PSD413A1-90U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ57230 with optional Total Dose Rating of 1000kRads
PSD413A2-12J Field-Programmable Peripheral
相關代理商/技術參數
參數描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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