參數(shù)資料
型號(hào)： PSD413A1F
英文描述： Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入）
文件頁(yè)數(shù)： 64/98頁(yè)
文件大小： 365K
代理商： PSD413A1F
PSD413F Family
6-64
ADVANCE INFORMATION
Reset Input
The reset input to the PSD413F (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD413F remains in
reset during T2 range. (See Figure 40). The PSD413F must be reset at power up before it
can be used.
ZPLD and Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The Boot EPROM and Flash memory blocks respond to the microcontroller bus
cycle during reset, but the data is not guaranteed.
Register Values During and After Reset
Table 21 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
ZPLD Macrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user in PSDabel, or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
Register Name
Device
Reset State
Control
Port A, B, C, D, E
Set to “0”
(Address Out Mode)
Data Out
(data or address)
Port A, B, C, D, E
Set to “0”
Direction
Port A, B, C, D, E
Set to “0” – Input Mode
Open Drain
Port C, D
Set to “0” – CMOS Outputs
Page Register
Page Logic
Set to “0”
PMMR0, PMMR1
Power Management Unit
Set to “0”
System
Configuration
(Cont.)
Table 21. Registers Reset Values
Port Configuration
Reset
Stand-by Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Tri-stated
*
Not Defined
Tri-stated
*
Data Port
Table 22. I/O Pin Status During Reset and Standby Mode
*
Data Port is in output mode if Boot EPROM, CSIOP or Flash memory is selected and Read pin is active.
相關(guān)PDF資料
PDF描述
PSD413F Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD413A2F Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入)
PSD4235G2(中文) Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
PSD4235G2 Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片)
PSD4235G2 FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS (5V SUPPLY)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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