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參數(shù)資料
| 型號： | PSD413A2-15JI |
| 英文描述： | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-3 package; Similar to IRHNB7160 with optional Total Dose Rating of 300kRads |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 29/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD413A2-15JI |
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PSD4XX Famly
26
The PSD4XX
Architecture
(cont.)
9.1.2.2 The GPLD
The structure of the General Purpose PLD consists of a programmable AND ARRAY and
3 sets of I/O Macrocells. The ARRAY has 59 input signals, same as the DPLD. From these
inputs, “ANDed” functions are generated as product term inputs to the macrocells. The I/O
Macrocell sets are named after the I/O Ports they are linked to, e.g., the macrocells
connected to Port A are named PA Macrocells. The 3 sets of macrocells, PA, PB and PE,
are similar in structure and function.
Figure 13 shows the output/input path of a GPLD macrocell to the Port pin with which it is
associated. If the Port pin is specified as a GPLD output pin in PSDsoft, the MUX in the I/O
Port Cell selects the GPLD macrocell as an output of the Port pin. The output enable signal
to the buffer in the I/O cell can be controlled by a product term from the AND ARRAY.
If the Port pin is specified as a ZPLD input pin, the MUX in the GPLD macrocell selects the
Port input signal to be one of the 61 signals in the ZPLD Input Bus.
9.1.2.3 Port A Macrocell Structure
Figure 14 shows the PA Macrocell block, which consists of 8 identical macrocells.
Each macrocell output can be connected to its own I/O pin on Port A. There are 3 user
programmable global product terms output from the GPLD’s AND ARRAY which are
shared by all the macrocells in Port A:
J
PA.OE
Enable or tri-state Port A output pins
J
PA.PR
Preset D flip flop in the macrocells
J
PA.RE
Reset/Clear D flip flop in the macrocells
Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip
flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as
the Reset input pin except it is user configurable.
The circuit of a PA Macrocell is shown in Figure 15. There are 6 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the
output, and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop
J
Combinatorial Output
Select output from OR gate
J
GPLD Input
Use Port A pin as dedicated input
J
GPLD Output
Use Port A pin as dedicated output
J
GPLD I/O
Use Port A pin as bidirectional pin
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback from
the combinatorial output, to expand the number of product terms available to another
macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected to a
Port A pin, Port A can be configured to perform other user defined I/O functions.
The two global product terms assigned for asynchronous clear (PA.RE) and preset (PA.PR)
are mainly for proper PA Macrocell initialization. The macrocell flip-flop can also be cleared
during reset by MACRO-RST, if such an option is chosen. The clock source is always the
input clock CLKIN.
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| PSD413A2-20JI | Field-Programmable Peripheral |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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