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參數資料
| 型號： | PSD413A2-90U |
| 英文描述： | 400V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; A IRHNA7360SE with Standard Packaging |
| 中文描述： | 現場可編程外圍 |
| 文件頁數： | 68/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD413A2-90U |
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PSD4XX Famly
65
The PSD4XX
Architecture
(cont.)
Figure 34. Port A In Peripheral I/OMode
RD
PSEL0
PSEL1
D0 – D7
WR
PA0 – PA7
9.4.5 Peripheral I/O
The Peripheral I/O Mode is one of the operating modes of Port A. In this mode, Port A
is connected to the data bus of peripheral devices. Port A is enabled only when
the microcontroller is accessing the devices, otherwise the Port is tri-stated. This feature
enables the microcontroller to access external devices without requiring buffers and
decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode.
The memory address space occupied by the devices are defined by two signals: PSEL0
and PSEL1. The signals are direct outputs from the Decoding PLD (DPLD). Whenever any
of the signals is active, the Port A driver is enabled, and the direction of the data flow is
determined by the RD/WR signals.
The Peripheral I/O Mode and the peripheral select signals are configured and defined in the
PSDsoft Software (see the section on I/O Port for configuration). The PIO bit in the VM
Register (see Table 17) also needs to be set to “1” by the user to initialize the Peripheral I/O
Mode.
The Peripheral I/O mode can be used, for example, in DMA applications where the
microcontroller does not support DMA operations, such as tri-stating the address/data bus.
Figure 35 shows a block diagram of a microcontroller and PSD4XX based design that
makes use of this mode. In this application, the microcontroller has a multiplexed bus which
is connected to the ADIO port. The C and D ports connect to the peripheral address bus
and are both configured in Address Out Mode. Port A is configured in the Peripheral I/O
mode and is connected to the peripheral data bus. Ports B and E are used to generate
control signals.
During normal activity, the microcontroller has access to any peripheral (memory or I/O
device) through the PSD4XX device. When there is a DMA request, the
microcontroller tri-states the address bus on Ports C and D by writing a “0” to the port
Direction Registers. The DMA controller then takes over the data and address buses after
receiving acknowledgement from the microcontroller.
相關PDF資料 |
PDF描述 |
|---|---|
| PSD413A1 | Low Cost Field Programmable Microcontroller Peripherals |
| PSD402A1 | Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A2 | Low Cost Field Programmable Microcontroller Peripherals |
| PSD413A2 | Low Cost Field Programmable Microcontroller Peripherals |
| PSD412A1-C-70U | Low Cost Field Programmable Microcontroller Peripherals |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD413A2-C-70L | 制造商:WSI 功能描述: |
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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