參數(shù)資料
型號(hào)： PSD4235F2-A-12UI
廠商： 意法半導(dǎo)體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù)： 59/89頁(yè)
文件大小： 703K
代理商： PSD4235F2-A-12UI
59/89
PSD4235G2
POWER MANAGEMENT
The PSD device offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
I
All memory blocks in a PSD (primary Flash
memory, secondary Flash memory, and SRAM)
are built with power management technology. In
addition to using special silicon design
methodology, power management technology
puts the memories into standby mode when
address/data inputs are not changing (zero DC
current). As soon as a transition occurs on an
input, the affected memory “wakes up”,
changes and latches its outputs, then goes back
to standby. The designer does
not
have to do
anything special to achieve memory Stand-by
mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as de-
scribed for the Power Management Mode Reg-
isters (PMMR), later.
I
The Automatic Power Down (APD) block allows
the PSD to reduce to stand-by current
automatically. The APD Unit also blocks MCU
address/data signals from reaching the
memories and PLDs. This feature is available
on all PSD devices. The APD Unit is described
in more detail in the section entitled “APD Unit”,
on page 60.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain period (the MCU is asleep), the APD Unit
initiates Power-down mode (if enabled). Once in
Power-down mode, all address/data signals are
blocked from reaching the PSD memories and
PLDs, and the memories are deselected inter-
nally. This allows the memories and PLDs to re-
main in Stand-by mode even if the address/data
signals are changing state externally (noise,
other devices on the MCU bus, etc.). Keep in
mind that any unblocked PLD input signals that
are changing states keeps the PLD out of
Stand-by mode, but not the memories.
I
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in Stand-by mode even if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit, especially if your MCU
has a chip select output. There is a slight
penalty in memory access time when PSD Chip
Select Input (CSI, PD2) makes its initial
transition from deselected to selected.
I
The Power Management Mode Registers
(PMMR) can be written by the MCU at run-time
to manage power. All PSD devices support
“blocking bits” in these registers that are set to
block designated signals from reaching both
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs (see Figure 35).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations at run-time. PSDsoft Ex-
press creates a fuse map that automatically
blocks the low address byte (A7-A0) or the con-
trol signals (CNTL0-CNTL2, ALE and Write En-
able High-byte (WRH/DBE, PD3)) if none of
these signals are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This
bit can be set to turn the Turbo mode off (the de-
fault is with Turbo mode turned on). While Turbo
mode is off, the PLDs can achieve Stand-by cur-
rent when no PLD inputs are changing (zero DC
current). Even when inputs do change, signifi-
cant power can be saved at lower frequencies
(AC current), compared to when Turbo mode is
on. When the Turbo mode is on, there is a sig-
nificant DC current component, and the AC
component is higher.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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