參數(shù)資料
型號： PSD4235F2-B-70J
廠商： 意法半導(dǎo)體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù)： 6/89頁
文件大?。?/td> 703K
代理商： PSD4235F2-B-70J
PSD4235G2
6/89
Figure 3. TQFP Connections
In-Application Programming (IAP)
Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture.
Designers are relieved of these problems:
Simultaneous read and write to Flash memo-
ry.
How can the MCU program the same memory
from which it executing code It cannot. The PSD
allows the MCU to operate the two Flash memory
blocks concurrently, reading code from one while
erasing and programming the other during IAP.
Complex memory mapping.
How can I map
these two memories efficiently A programmable
Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space.
How can I
write to Flash memory while it resides in Program
space during field firmware updates My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
60 CNTL1
59 CNTL0
58 PA7
57 PA6
56 PA5
55 PA4
54 PA3
53 PA2
52 PA1
51 PA0
50 GND
49 GND
48 PC7
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46 PC5
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42 PC1
41 PC0
PD2
PD3
AD0
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VCC
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AI04943
相關(guān)PDF資料
PDF描述
PSD4235F2-B-70JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235F2-B-70M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235F2-B-70MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235F2-B-70U Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235F2-B-70UI Flash In-System-Programmable Peripherals for 16-Bit MCUs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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