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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD4235F3-A-70B81I

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
中文描述：
Flash在系統(tǒng)可編程外設(shè)的16位微控制器

    

    
文件頁(yè)數(shù)：
63/93頁(yè)

    

    
文件大?。?/td>
503K

    

    
代理商：
PSD4235F3-A-70B81I


    

    

    

	
    
    
    

    
    
	
    PSD4000 Series
    Preliminary Information
    60
    The 
    PSD4000
    Functional
    Blocks
    (cont.)
    9.5.3   Reset and Power On Requirement
    9.5.3.1  Power On Reset
    Upon power up the PSD4000 requires a reset pulse of tNLNH-PO (minimum 1 ms) after 
    V
    CC
    is steady. During this time period the device loads internal configurations, clears 
    some of the registers and sets the Flash into operating mode. After the rising edge of
    reset, the PSD4000 remains in the reset state for an additional tOPR (maximum 120 ns)
    nanoseconds before the first memory access is allowed.
    The PSD4000 Flash memory is reset to the read array mode upon power up. The FSi 
    and CSBOOTi select signals along with the write strobe signal must be in the false 
    state during power-up reset for maximum security of the data contents and to remove 
    the possibility of data being written on the first edge of a write strobe signal. Any Flash
    memory write cycle initiation is prevented automatically when V
    CC
    is below VLKO.
    9.5.3.2  Warm Reset
    Once the device is up and running, the device can be reset with a much shorter pulse of 
    tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
    after warm reset. Figure 26 shows the timing of the power on and warm reset.
    OPERATING LEVEL
    POWER ON RESET
    V
    CC
    RESET
    tNLNH
    –
    PO
    tOPR
    tNLNH-A
    tNLNH
    tOPR
    WARM
    RESET
    Figure 26.  Power On and Warm Reset Timing
    9.5.3.3  
    I/OPin, Register and PLD Status at Reset
    Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset 
    and power down mode. PLD outputs are always valid during warm reset, and they are
    valid in power on reset once the internal PSD configuration bits are loaded. This loading of
    PSD is completed typically long before the V
    CC
    ramps up to operating level. Once the PLD
    is active, the state of the outputs are determined by the equations specified in PSDsoft.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD4235F3-A-70J
Tantalum Electrolytic Capacitor; Capacitance:1uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:20V; Package/Case:3216-18; Terminal Type:PCB SMT; ESR:10ohm; Mounting Type:Surface Mount; Operating Temp. Max:85 C

    

    
PSD4235F3-A-70JI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4235F3-A-70M
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4235F3-A-70MI
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    
PSD4235F3-A-70U
Flash In-System-Programmable Peripherals for 16-Bit MCUs

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD4235G2-70U
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD4235G2-90U
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD4235G2-90UI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD4235G2V-12UI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD4235G2V-90U
功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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