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參數(shù)資料
| 型號(hào)： | PSD4235F3-C-15UI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁(yè)數(shù)： | 60/89頁(yè) |
| 文件大?。?/td> | 703K |
| 代理商： | PSD4235F3-C-15UI |
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PSD4235G2
60/89
Figure 32. APD Unit
Automatic Power-down (APD) Unit and Power-
down Mode.
The APD Unit, shown in Figure 32,
puts the PSD into Power-down mode by monitor-
ing the activity of Address Strobe (ALE/AS, PD0).
If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit
counter starts counting. If Address Strobe (ALE/
AS, PD0) remains inactive for fifteen clock periods
of CLKIN (PD1), Power-down (PDN) goes High,
and the PSD enters Power-down mode, as dis-
cussed next.
Table 48. Effect of Power-down Mode on Ports
Power-down Mode.
By default, if you enable the
APD Unit, Power-down mode is automatically en-
abled. The device enters Power-down mode if Ad-
dress Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
I
If Address Strobe (ALE/AS, PD0) starts pulsing
again, the PSD returns to normal operation. The
PSD also returns to normal operation if either
PSD Chip Select Input (CSI, PD2) is Low or the
Reset (RESET) input is High.
I
The MCU address/data bus is blocked from all
memory and PLDs.
I
Various signals can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the Power Management
Mode Registers (PMMR). The blocked signals
include MCU control signals and the common
CLKIN (PD1). Note that blocking CLKIN (PD1)
from the PLDs does not block CLKIN (PD1)
from the APD Unit.
I
All PSD memories enter Stand-by mode and are
drawing Stand-by current. However, the PLDs
and I/O ports blocks do not
go into Stand-by
mode because you do not want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 48 for Power-
down mode effects on PSD ports.
I
Typical Stand-by current is or the order of μA.
This Stand-by current value assumes that there
are no transitions on any PLD input.
Table 49. PSD Timing and Stand-by Current during Power-down Mode
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption, see Table 60, assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN) Select
DISABLE BUS
INTERFACE
Secondary Flash
Memory Select
Primary Flash
SRAM Select
PD
CLR
PD
DISABLE Primary and Secondary
FLASH Memory and SRAM
PLD
AI04939
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Tri-State
Peripheral I/O
Tri-State
Mode
PLD Propagation Delay
Memory Access
Time
Access Recovery Time to
Normal Access
Typical Stand-by
Current
Power-down
Normal t
PD
(Note
1
)
No Access
t
LVDV
I
SB
(Note
2
)
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| PSD4235G1-B-15B81 | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
| PSD4235G1-B-15B81I | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G1-B-15J | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G1-B-15JI | Tantalum Electrolytic Capacitor; Capacitance:2.2uF; Capacitance Tolerance:+/- 10 %; Working Voltage, DC:16V; Package/Case:3216-18; Terminal Type:PCB SMT; ESR:6ohm; Leaded Process Compatible:No; Mounting Type:Surface Mount |
| PSD4235G1-B-15M | CAP, TANT 2.2MF 16V 10% SMD |
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