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    參數(shù)資料
    型號(hào)： PSD4235G1V-C-70B81
    廠商： 意法半導(dǎo)體
    英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
    文件頁(yè)數(shù)： 19/93頁(yè)
    文件大?。?/td> 503K
    代理商： PSD4235G1V-C-70B81
    PSD4000 Series
    Preliminary Information
    16
    9.1.1.3 Memory Operation
    The main Flash and secondary Flash memories are addressed through the microcontroller
    interface on the PSD4000 device. The microcontroller can access these memories in one
    of two ways:
    J
    The microcontroller can execute a typical bus write or read
    operation
    just as it would
    if accessing a RAM or ROM device using standard bus cycles.
    J
    The microcontroller can execute a specific
    instruction
    that consists of several write
    and read operations. This involves writing specific data patterns to special addresses
    within the Flash to invoke an embedded algorithm. These instructions are summarized
    in Table 8.
    Typically, Flash memory can be read by the microcontroller using read operations, just
    as it would read a ROM device. However, Flash memory can only be erased and
    programmed with specific instructions. For example, the microcontroller cannot write a
    single word directly to Flash memory as one would write a word to RAM. To program a
    word into Flash memory, the microcontroller must execute a program instruction sequence,
    then test the status of the programming event. This status test is achieved by a read
    operation or polling the Rdy/Busy pin (PE4).
    The Flash memory can also be read by using special instructions to retrieve particular
    Flash device information (sector protect status and ID).
    9.1.1.3.1 Instructions
    An instruction is defined as a sequence of specific operations. Each received byte is
    sequentially decoded by the PSD and not executed as a standard write operation. The
    instruction is executed when the correct number of bytes are properly received and the
    time between two consecutive bytes is shorter than the time-out value. Some instructions
    are structured to include read operations after the initial write operations.
    The sequencing of any instruction must be followed exactly. Any invalid combination of
    instruction bytes or time-out between two consecutive bytes while addressing Flash
    memory will reset the device logic into a read array mode (Flash memory reads like a
    ROM device).
    The PSD4000 main Flash and secondary Flash support these instructions (see Table 8):
    J
    Erase memory by chip or sector
    J
    Suspend or resume sector erase
    J
    Program a word
    J
    Reset to read array mode
    J
    Read Main Flash Identifier value
    J
    Read sector protection status
    J
    Bypass Instruction
    These instructions are detailed in Table 8. For efficient decoding of the instructions, the
    first two bytes of an instruction are the coded cycles and are followed by a command byte
    or confirmation byte. The coded cycles consist of writing the data byte AAh to address
    XAAAh during the first cycle and data byte 55h to address X554h during the second cycle
    (unless the Bypass Instruction feature is used. See 9.1.1.7). Address lines A15-A12 are
    don’t care during the instruction write cycles. However, the appropriate sector select signal
    (FSi or CSBOOTi) must be selected.
    The main Flash and the secondary Flash Block have the same set of instructions (except
    Read main Flash ID). The chip selects of the Flash memory will determine which Flash will
    receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is
    active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.
    The
    PSD4000
    Functional
    Blocks
    (cont.)
    相關(guān)PDF資料
    PDF描述
    PSD4235G1V-C-70B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G1V-C-70J Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G1V-C-70JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G1V-C-70M Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G1V-C-70MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD4235G2-70U 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
    PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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