參數(shù)資料
型號： PSD4235G2-12JI
廠商： 意法半導(dǎo)體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù)： 64/93頁
文件大小： 503K
代理商： PSD4235G2-12JI
9.5.3.4 Reset of Flash Erase and Programming Cycles
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 μs) time.
9.6 Programming In-Circuit using the JTAG-ISP Interface
The JTAG-ISP interface on the PSD4000 can be enabled on Port E (see Table 29). All
memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG-ISC interface. A blank part can be mounted on a printed
circuit board and programmed using JTAG-ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
Preliminary Information
PSD4000 Series
61
Port E Pin
PE0
PE1
PE2
PE3
PE4
PE5
JTAG Signals
TMS
TCK
TDI
TDO
TSTAT
TERR
Description
Mode Select
Clock
Serial Data In
Serial Data Out
Status
Error Flag
Table 29. JTAG Port Signals
The
PSD4000
Functional
Blocks
(cont.)
*
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
Port Configuration
MCU I/O
PLD Output
Power On Reset
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Address Out
Data Port
Tri-stated
Tri-stated
Table 28. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Cleared to
“
0
”
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Warm Reset
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Power Down Mode
Unchanged
Unchanged
PMMR0, 2
VM Register*
All other registers
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note 54 for more details on JTAG In-System-Programming.
相關(guān)PDF資料
PDF描述
PSD4135G2-12M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-12M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135G2-12MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-12MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4135F2V-12B81I Header; No. of Contacts:80; Pitch Spacing:2.54mm; No. of Rows:2; Series:C-Grid III; Connector Body Material:Polyester; Mounting Type:PC Board; Terminal Type:Straight Pin RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2-90UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-12UI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD4235G2V-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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