參數(shù)資料
型號(hào): PSD4235G2-A-12UI
廠商: 意法半導(dǎo)體
英文描述: CAP 3.3UF 4V 20% TANT SMD-3216-18 TR-7-PL SN/PB5%
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù): 65/89頁(yè)
文件大?。?/td> 703K
代理商: PSD4235G2-A-12UI
65/89
PSD4235G2
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD4235G2:
J
DC Electrical Specification
J
AC Timing Specification
I
PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
I
MCU Timing
– Read Timing
– Write Timing
– Peripheral Mode Timing
– Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
I
In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo bit is 0.
I
The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 35 show the PLD mA/MHz as a function
of the number of Product Terms (PT) used.
I
In the PLD timing parameters, add the required
delay when Turbo bit is 0.
Figure 35. PLD I
CC
/Frequency Consumption
AI05739
0
10
20
30
40
50
60
70
80
90
100
110
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
I
PT 100%
PT 25%
Vcc = 5V
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
相關(guān)PDF資料
PDF描述
PSD4235G2-A-70J CAP 3.3UF 20V 20% TANT SMD-3216-18 TR-13-PL SN100%
PSD4235G2-A-70JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-A-70M Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-A-70MI CAP 33UF 3V 10% TANT SMD-3216-18 TR-13-PL GOLD
PSD4235G2-A-70U Flash In-System-Programmable Peripherals for 16-Bit MCUs
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