參數(shù)資料
型號: PSD4235G2-B-70M
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的16位微控制器5V電源
文件頁數(shù): 56/89頁
文件大?。?/td> 703K
代理商: PSD4235G2-B-70M
PSD4235G2
56/89
Figure 29. Port A, B and C Structure
Enable Out.
The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A 1 indicates the driver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.
Ports A, B and
C – Functionality and Structure
Ports A, B and C have similar functionality and
structure, as shown in Figure 29. The ports can be
configured to perform one or more of the following
functions:
I
MCU I/O Mode
I
C
PLD Output – Macrocells McellA7-McellA0
can be connected to Port A. McellB7-McellB0
can be connected to Port B. External Chip
Select (ECS7-ECS0) can be connected to Port
C or Port F.
I
CPLD Input – Via the Input Macrocells (IMC).
I
Address In – Additional high address inputs
using the Input Macrocells (IMC).
I
Open Drain/Slew Rate – pins PC7-PC0 can be
configured to fast slew rate. Pins PA7-PA0 can
be configured to Open Drain mode.
I
DATA OUT
Register
D
Q
D
Q
WR
MCELL7-MCELL0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR Register
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
AI04936
相關(guān)PDF資料
PDF描述
PSD4235G2-B-70MI CAP 0.47UF 25V 20% TANT SMD-3216-18 TR-7-PL GOLD
PSD4235G2-B-70U Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2-B-70UI CAP 0.47UF 25V 20% TANT SMD-3216-18 TR-7-PL SN100%
PSD4235G2-C-70U Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-C-70UI CAP 4.7UF 4V 20% TANT SMD-3216-18 TR-13-PL SN100%
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