參數(shù)資料
型號(hào): PSD4235G2-B-70U
廠商: 意法半導(dǎo)體
英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁數(shù): 30/89頁
文件大小: 703K
代理商: PSD4235G2-B-70U
PSD4235G2
30/89
Figure 10. 8031 Memory M
odules – Combined Space
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
Select (FS0-FS7,
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154
Table 22 and Figure 11 show the Page Register.
The eight flip-flops in the register are connected to
the internal data bus (D0-D7). The MCU can write
to or read from the Page Register. The Page Reg-
ister can be accessed at address location CSIOP
+ E0h.
Figure 11. Page Register
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
RD
CS
CS
CS
RD
OE
OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI02870C
RESET
D0 - D7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B
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