參數(shù)資料
型號(hào): PSD4235G2-B-70UI
廠商: 意法半導(dǎo)體
英文描述: CAP 0.47UF 25V 20% TANT SMD-3216-18 TR-7-PL SN100%
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù): 29/89頁(yè)
文件大?。?/td> 703K
代理商: PSD4235G2-B-70UI
29/89
PSD4235G2
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note that an equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would not
be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces.
The
80C51XA and compatible family of MCUs, can be
configured to have separate address spaces for
Program memory (selected using Program Select
Enable (PSEN, CNTL2)) and Data memory (se-
lected using Read Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
Express to configure it for Boot-up and having the
MCU change it when desired.
Table 25 describes the VM Register.
Separate Space Modes.
Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 9).
Figure 9. 8031 Memory
Modules – Separate Space
Combined Space Modes.
The
Data spaces are combined into one memory
space that allows the primary Flash memory, sec-
ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
Program
and
configure the primary Flash memory in Combined
space, bits 2 and 4 of the VM register are set to 1
(see Figure 10).
80C51XA Memory Map Example.
See the Ap-
plication Notes for examples.
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
CS
CS
CS
OE
OE
RD
PSEN
OE
AI02869C
相關(guān)PDF資料
PDF描述
PSD4235G2-C-70U Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G2-C-70UI CAP 4.7UF 4V 20% TANT SMD-3216-18 TR-13-PL SN100%
PSD4235G3-A-15B81 CAP 47UF 6.3V 20% TANT SMD-3216-18 TR-13-PL SN100%
PSD4235G3-A-15B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G3-A-15J Flash In-System-Programmable Peripherals for 16-Bit MCUs
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