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參數(shù)資料
| 型號： | PSD4235G2-C-70U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的16位微控制器5V電源 |
| 文件頁數(shù)： | 11/89頁 |
| 文件大?。?/td> | 703K |
| 代理商： | PSD4235G2-C-70U |
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PSD4235G2
PIN DESCRIPTION
Table 5 describes the signal names and signal
functions of the PSD. Those that have multiple
names or functions are defined using PSDsoft Ex-
press.
Table 5. Pin Description (for the TQFP package)
Pin Name
Pin
Type
Description
ADIO0-
ADIO7
3-7
10-12
I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
ADIO8-
ADIO15
13-20
I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the upper address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
CNTL0
59
I
The following control signals can be connected to this pin, based on your MCU:
1. WR
– active Low, Write Strobe input.
2. R_W – active High, read/active Low write input.
3. WRL – active Low, Write to Low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL1
60
I
The following control signals can be connected to this pin, based on your MCU:
1. RD – active Low, Read Strobe input.
2. E – E clock input.
3. DS – active Low, Data Strobe input.
4. LDS – active Low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL2
40
I
Read or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN – Program Select Enable, active Low in code fetch bus cycle (80C51XA
mode).
2. BHE – High-byte enable, 16-bit data bus.
3. UDS – active Low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 – Byte enable input.
5. LSTRB – Low Strobe input.
This pin is also connected to the PLDs.
Reset
39
I
Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
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| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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