參數(shù)資料
型號(hào): PSD4235G2-C-70UI
廠商: 意法半導(dǎo)體
英文描述: CAP 4.7UF 4V 20% TANT SMD-3216-18 TR-13-PL SN100%
中文描述: Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù): 78/89頁(yè)
文件大?。?/td> 703K
代理商: PSD4235G2-C-70UI
PSD4235G2
78/89
Table 66. Write Timing
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
7. tWHAX is 6 ns when writing to the Output Macrocell Registers AB and BC.
Symbol
Parameter
Conditions
-70
-90
Unit
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
15
20
ns
t
AVLX
Address Setup Time
(Note
1
)
4
6
ns
t
LXAX
Address Hold Time
(Note
1
)
7
8
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes
1,3
)
8
15
ns
t
SLWL
CS Valid to Leading Edge of WR
(Note
3
)
12
15
ns
t
DVWH
WR Data Setup Time
(Note
3
)
25
35
ns
t
WHDX
WR Data Hold Time
(Note
3,7
)
4
5
ns
t
WLWH
WR Pulse Width
(Note
3
)
28
35
ns
t
WHAX1
Trailing Edge of WR to Address Invalid
(Note
3
)
6
8
ns
t
WHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note
3,6
)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note
3
)
27
30
ns
t
DVMV
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes
3,5
)
42
55
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note
2
)
20
25
ns
t
WLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes
3,4
)
48
55
ns
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