參數資料
型號: PSD4235G2V-A-90B81I
廠商: 意法半導體
英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述: Flash在系統(tǒng)可編程外設的16位微控制器
文件頁數: 25/93頁
文件大?。?/td> 503K
代理商: PSD4235G2V-A-90B81I
The
PSD4000
Functional
Blocks
(cont.)
MAIN
FLASH
DPLD
FLASH
BOOT
BLOCK
SRAM
RS0
CSBOOT0-3
FS0-7
CS
OE
RD
PSEN
OE
Figure 6. 80C51XA Memory Modes – Separate Space Mode
MAIN
FLASH
DPLD
FLASH
BOOT
BLOCK
SRAM
RS0
CSBOOT0-3
FS0-7
RD
CS
RD
OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
Figure 7. 80C51XA Memory Mode – Combined Space Mode
9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces
9.1.3.2.1 Separate Space Modes
Code memory space is separated from data memory space. For example, the PSEN
signal is used to access the program code from the main Flash Memory, while the RD
signal is used to access data from the secondary Flash memory, SRAM and I/O Ports.
This configuration requires the VM register to be set to 0Ch.
9.1.3.2.2 . Combined Space Modes
The program and data memory spaces are combined into one space that allows the main
Flash Memory, secondary Flash memory, and SRAM to be accessed by either PSEN or
RD. For example, to configure the main Flash memory in combined space mode, bits 2
and 4 of the VM register are set to “1”.
9.1.3.3 80C51XA Memory Map Example
See Application Notes for examples.
PSD4000 Series
Preliminary Information
28
相關PDF資料
PDF描述
PSD4235G2V-A-90J Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2V-A-90JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2V-A-90M CAP 150UF 10V 20% TANT SMD-7343-31 TR-7-PL SN100% LOWESR-0250
PSD4235G2V-B-15B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G2V-B-15B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
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