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參數(shù)資料
| 型號(hào)： | PSD4235G2V-B-15U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 28/93頁 |
| 文件大小： | 503K |
| 代理商： | PSD4235G2V-B-15U |
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Preliminary Information
PSD4000 Series
31
The
PSD4000
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD4000. After specifying the
logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon
power-up.
The PSD4000 contains two PLDs: the Decode PLD (DPLD), and the General Purpose
PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more
detail in sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The GPLD can be used to generate external chip selects, control signals or logic functions.
The GPLD has 24 outputs that are connected to Port A, B and C.
The AND array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 66 signals is connected to the PLDs. The signals are
shown in Table 12. The complement of the 66 signals are also available as inputs to the
AND array.
Input Source
Input Name
Number
of Signals
MCU Address Bus
A[15:0]
*
16
MCU Control Signals
CNTL[2:0]
3
Reset
RST
1
Power Down
PDN
1
Port A Input
PA[7-0]
8
Port B Input
PB[7-0]
8
Port C Input
PC[7-0]
8
Port D Inputs
PD[3:0]
4
Port F Inputs
PF[7:0]
8
Page Register
PGR(7:0)
8
Flash Programming Status Bit
Rdy/Bsy
1
Table 12. DPLD and GPLD Inputs
NOTE: The address inputs are A[19:4] in 80C51XA mode.
The Turbo Bit
The PLDs in the PSD4000 can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo
mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if
no inputs are changing. Turbo-off mode increases propagation delays while reducing
power consumption. Refer to the Power Management Unit section on how to set the Turbo
Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
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| PSD4235G2V-B-20B81 | Tantalum Electrolytic Capacitor; Capacitance:220uF; Capacitance Tolerance:+/- 20 %; Working Voltage, DC:10V; Package/Case:7343-31; Terminal Type:PCB SMT; ESR:0.004ohm; Dielectric Material:Tantalum; Operating Temp. Max:105 C |
| PSD4235G2V-B-70JI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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| PSD4235G2V-B-70MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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