參數(shù)資料
型號(hào)： PSD4235G2V-B-90J
廠商： 意法半導(dǎo)體
英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
中文描述： Flash在系統(tǒng)可編程外設(shè)的16位微控制器
文件頁(yè)數(shù)： 49/93頁(yè)
文件大小： 503K
代理商： PSD4235G2V-B-90J
PSD4000 Series
Preliminary Information
50
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 19, are used for setting the port configurations. The default power-up state
for each register in Table 22 is 00h.
Register Name
Port
MCU Access
Control
E,F,G
Write/Read
Direction
A,B,C,D,E,F,G
Write/Read
Drive Select*
A,B,C,D,E,F,G
Write/Read
Table 19. Port Configuration Registers
*NOTE: See Table 22 for Drive Register bit definition.
The
PSD4000
Functional
Blocks
(cont.)
9.4.3.1 Control Register
Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,
and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and
G have an associated Control Register.
9.4.3.2 Direction Register
The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corresponding pin to be an output, and any bit set
to ‘0’ will cause it to be an input. The default mode for all port pins is input.
Figures 21 and 23 show the Port Architecture diagrams for Ports A/B/C and E/F/G
respectively. The direction of data flow for Ports A, B, C and F are controlled by the
direction register.
An example of a configuration for a port with the three least significant bits set to output
and the remainder set to input is shown in Table 21. Since Port D only contains four pins,
the Direction Register for Port D has only the four least significant bits active.
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Table 20. Port Pin Direction Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
000
0
1
Table 21. Port Direction Assignment Example
相關(guān)PDF資料
PDF描述
PSD4235G2V-B-90JI Conductive Polymer Chip Capacitors / T520 Series - KO Cap; Capacitance [nom]: 330uF; Working Voltage (Vdc)[max]: 6.3V; Capacitance Tolerance: +/-20%; Dielectric: Conductive Polymer; ESR: 40mΩ; Lead Style: Surface-Mount Chip; Lead Dimensions: 7343-31; Termination: 100% Tin (Sn); Body Dimensions: 7.3mm x 4.3mm x 2.8mm; Temperature Range: -55C to +105C; Container: Tape & Reel; Qty per Container: 500; Features: Low ESR
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