參數(shù)資料
型號(hào): PSD8132V90JT
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 96/110頁(yè)
文件大?。?/td> 1685K
代理商: PSD8132V90JT
PSD813F1
96/110
Figure 50. Peripheral I/O WRITE Timing
Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 66. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode) signals.
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol
Parameter
Conditions
-90
-12
-15
Unit
Min
Max
Min
Max
Min
Max
t
WLQV
PA
WR to Data Propagation Delay
(Note
2
)
35
38
40
ns
t
DVQV
PA
Data to Port A Data Propagation Delay
(Note
5
)
30
35
38
ns
t
WHQZ
PA
WR Invalid to Port A Tri-state
(Note
2
)
25
30
33
ns
Symbol
Parameter
Conditions
-15
-20
Unit
Min
Max
Min
Max
t
WLQV
PA
WR to Data Propagation Delay
(Note
2
)
45
55
ns
t
DVQV
PA
Data to Port A Data Propagation Delay
(Note
5
)
40
45
ns
t
WHQZ
PA
WR Invalid to Port A Tri-state
(Note
2
)
33
35
ns
tDVQV (PA)
tWLQV (PA)
tWHQZ (PA)
ADDRESS
DATA OUT
A/D BUS
WR
PORT A
DATA OUT
ALE/AS
AI02898
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