參數(shù)資料
型號(hào)： PSD8134V12JT
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 90/110頁(yè)
文件大?。?/td> 1685K
代理商： PSD8134V12JT
PSD813F1
90/110
Table 56. READ Timing (3V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 20ns to t
AVQV
.
Symbol
Parameter
Conditions
-15
-20
Turbo
Off
Unit
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
26
30
ns
t
AVLX
Address Setup Time
(Note
3
)
10
12
ns
t
LXAX
Address Hold Time
(Note
3
)
12
14
ns
t
AVQV
Address Valid to Data Valid
(Note
3,6
)
150
200
+ 20
ns
t
SLQV
CS Valid to Data Valid
150
200
ns
t
RLQV
RD to Data Valid 8-Bit Bus
(Note
5
)
35
40
ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
(Note
2
)
50
55
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
0
ns
t
RLRH
RD Pulse Width (also DS, LDS, UDS)
40
45
ns
RD or PSEN Pulse Width (8031, 80251)
55
60
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
40
45
ns
t
EHEL
E Pulse Width
45
52
ns
t
THEH
R/W Setup Time to Enable
18
20
ns
t
ELTL
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
4
)
35
40
ns
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