參數(shù)資料
型號(hào): PSD8135V70MT
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Enhanced High Power Factor Preregulator 16-SOIC 0 to 70
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 89/110頁(yè)
文件大?。?/td> 1685K
代理商: PSD8135V70MT
89/110
PSD813F1
Table 55. READ Timing (5V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
6. In Turbo Off mode, add 10ns to t
AVQV
.
Symbol
Parameter
Conditions
-90
-12
-15
Turbo
Off
Unit
Min
Max
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
20
22
28
ns
t
AVLX
Address Setup Time
(Note
3
)
6
8
10
ns
t
LXAX
Address Hold Time
(Note
3
)
8
9
11
ns
t
AVQV
Address Valid to Data Valid
(Notes
3,6
)
90
120
150
+ 10
ns
t
SLQV
CS Valid to Data Valid
100
135
150
ns
t
RLQV
RD to Data Valid 8-Bit Bus
(Note
5
)
32
35
40
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note
2
)
38
42
45
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
0
0
ns
t
RLRH
RD Pulse Width
(Note
1
)
32
35
38
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
25
35
38
ns
t
EHEL
E Pulse Width
32
36
38
ns
t
THEH
R/W Setup Time to Enable
10
13
18
ns
t
ELTL
R/W Hold Time After Enable
0
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
4
)
25
28
32
ns
相關(guān)PDF資料
PDF描述
PSD8135V90MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A Enhanced High Power Factor Preregulator 16-PDIP 0 to 70
PSD813F1-A-12JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A-12MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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