參數(shù)資料
型號(hào)： PSD813F1-A-12MI
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 34/110頁(yè)
文件大?。?/td> 1685K
代理商： PSD813F1-A-12MI
PSD813F1
34/110
PLD
’
S
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using the PSDabel tool in PSDsoft Express, the
logic is programmed into the device and available
upon power-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the sections entitled
DE-
CODE PLD (DPLD)
and
COMPLEX PLD (CPLD)
.
Figure 15., page 35
shows the configuration of the
PLDs.
The DPLD performs address decoding for internal
and external components, such as memory, regis-
ters, and I/O port selects.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output macrocells (OMCs), 24 Input macrocells
(IMCs), and the AND array. The CPLD can also be
used to generate external chip selects.
The AND array is used to form product terms.
These product terms are specified using PSDabel.
An Input Bus consisting of 73 signals is connected
to the PLDs. The signals are shown in Table
13
.
The Turbo Bit in PSD
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns.
Setting the Turbo mode bit to off (Bit 3 of the
PMMR0 register) automatically places the PLDs
into standby if no inputs are changing. Turbo-off
mode increases propagation delays while reduc-
ing power consumption. See the section entitled
POWER MANAGEMENT, page 64
, on how to set
the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
The PLDs in the PSD can minimize power con-
sumption by switching off when inputs remain un-
changed for an extended time of about 70ns. Each
of the two PLDs has unique characteristics suited
for its applications. They are described in the fol-
lowing sections.
Table 13. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
Input Source
Input Name
Number
of
Signals
MCU Address Bus
1
A15-A0
16
MCU Control Signals
CNTL2-CNTL0
3
Reset
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD2-PD0
3
Page Register
PGR7-PGR0
8
Macrocell AB
Feedback
MCELLAB.FB7-
FB0
8
Macrocell BC
Feedback
MCELLBC.FB7-
FB0
8
EEPROM Program
Status Bit
Ready/Busy
1
相關(guān)PDF資料
PDF描述
PSD813F1-A-90J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1A-90MI Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1A-90MT Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F1A-12MI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1A-12MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1A-12U 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1A-12UI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 120ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F1A-12UT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
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