- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄378074 > PSD813F1A-90MI (意法半導(dǎo)體) Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD813F1A-90MI |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| 中文描述： | Flash在系統(tǒng)可編程（ISP）的周邊8位MCU，5V的 |
| 文件頁(yè)數(shù)： | 15/110頁(yè) |
| 文件大?。?/td> | 1685K |
| 代理商： | PSD813F1A-90MI |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)
15/110
PSD813F1
JTAG Port
In-System Programming can be performed
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table
3
indicates the
JTAG signals pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller
executing
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table
4
indicates which programming
methods can program different functional blocks
of the PSD.
Page Register
The 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
the
programming
Power Management Unit (PMU)
The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the
section
MANAGEMENT, page 64
for more details.
entitled
POWER
Table 3. JTAG SIgnals on Port C
Table 4. Methods of Programming Different Functional Blocks of the PSD
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Functional Block
JTAG Programming
Device Programmer
In-System Parallel
Programming
Main Flash Memory
Yes
Yes
Yes
EEPROM Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Optional OTP Row
No
Yes
Yes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813F1A-90MT | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F1V | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2V-15 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F2V-20 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F2V-70 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F1A-90MT | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F1A-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD813F1A-90UI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD813F1A-90UT | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F1AV-12JIT | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。