參數(shù)資料
型號(hào)： PSD813F2-12JIT
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 15/110頁(yè)
文件大?。?/td> 1685K
代理商： PSD813F2-12JIT
15/110
PSD813F1
JTAG Port
In-System Programming can be performed
through the JTAG pins on Port C. This serial inter-
face allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table
3
indicates the
JTAG signals pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the microcontroller. The main Flash memo-
ry can also be programmed in-system by the mi-
crocontroller
executing
algorithms out of the EEPROM or SRAM. The EE-
PROM can be programmed the same way by exe-
cuting out of the main Flash memory. The PLD
logic or other PSD configuration can be pro-
grammed through the JTAG port or a device pro-
grammer. Table
4
indicates which programming
methods can program different functional blocks
of the PSD.
Page Register
The 8-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the ad-
dress space to access external memory and pe-
ripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit programming.
the
programming
Power Management Unit (PMU)
The Power Management Unit (PMU) in the PSD
gives the user control of the power consumption
on selected functional blocks based on system re-
quirements. The PMU includes an Automatic Pow-
er Down unit (APD) that will turn off device
functions due to microcontroller inactivity. The
APD unit has a Power Down Mode that helps re-
duce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The turbo bit in the PMMR0 reg-
ister can be turned off and the CPLD will latch its
outputs and go to sleep until the next transition on
its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the
section
MANAGEMENT, page 64
for more details.
entitled
POWER
Table 3. JTAG SIgnals on Port C
Table 4. Methods of Programming Different Functional Blocks of the PSD
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Functional Block
JTAG Programming
Device Programmer
In-System Parallel
Programming
Main Flash Memory
Yes
Yes
Yes
EEPROM Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Optional OTP Row
No
Yes
Yes
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