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      參數(shù)資料
      型號(hào): PSD833270JT
      廠商: 意法半導(dǎo)體
      英文描述: High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
      中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
      文件頁數(shù): 1/110頁
      文件大?。?/td> 1737K
      代理商: PSD833270JT
      1/110
      PRELIMINARY DATA
      June 2004
      This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
      PSD813F2, PSD833F2
      PSD834F2, PSD853F2, PSD854F2
      Flash In-System Programmable (ISP)
      Peripherals for 8-bit MCUs, 5V
      FEATURES SUMMARY
      FLASH IN-SYSTEM PROGRAMMABLE (ISP)
      PERIPHERAL FOR 8-BIT MCUS
      DUAL BANK FLASH MEMORIES
      UP TO 2 Mbit OF PRIMARY FLASH
      MEMORY (8 Uniform Sectors, 32K x8)
      UP TO 256 Kbit SECONDARY FLASH
      MEMORY (4 Uniform Sectors)
      Concurrent operation: READ from one
      memory while erasing and writing the
      other
      UP TO 256 Kbit BATTERY-BACKED SRAM
      27 RECONFIGURABLE I/O PORTS
      ENHANCED JTAG SERIAL PORT
      PLD WITH MACROCELLS
      Over 3000 Gates of PLD: CPLD and
      DPLD
      CPLD with 16 Output Macrocells (OMCs)
      and 24 Input Macrocells (IMCs)
      DPLD - user defined internal chip select
      decoding
      27 INDIVIDUALLY CONFIGURABLE I/O
      PORT PINS
      The can be used for the following functions:
      MCU I/Os
      PLD I/Os
      Latched MCU address output
      Special function I/Os.
      16 of the I/O ports may be configured as
      open-drain outputs.
      IN-SYSTEM PROGRAMMING (ISP) WITH
      JTAG
      Built-in JTAG compliant serial port allows
      full-chip In-System Programmability
      Efficient manufacturing allow easy
      product testing and programming
      Use low cost FlashLINK cable with PC
      PAGE REGISTER
      Internal page register that can be used to
      expand the microcontroller address space
      by a factor of 256
      PROGRAMMABLE POWER MANAGEMENT
      Figure 1. Packages
      HIGH ENDURANCE:
      100,000 Erase/WRITE Cycles of Flash
      Memory
      1,000 Erase/WRITE Cycles of PLD
      15 Year Data Retention
      5V±10% SINGLE SUPPLY VOLTAGE
      STANDBY CURRENT AS LOW AS 50μA
      PQFP52 (M)
      PLCC52 (J)
      TQFP64 (U)
      相關(guān)PDF資料
      PDF描述
      PSD833270MIT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
      PSD833270MT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
      PSD833290MT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
      PSD8332V12JT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
      PSD8332V12MIT High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      PSD833F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
      PSD833F2-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
      PSD833F2-90M 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
      PSD833F2-90MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
      PSD834F2-15M 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP