- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376268 > PSD834F3V-15 (意法半導(dǎo)體) High Speed Voltage Mode Pulse Width Modulator 8-SOIC -40 to 85 PDF資料下載
參數(shù)資料
| 型號(hào)： | PSD834F3V-15 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | High Speed Voltage Mode Pulse Width Modulator 8-SOIC -40 to 85 |
| 中文描述： | Flash在系統(tǒng)可編程（ISP）的周邊8位MCU，5V的 |
| 文件頁(yè)數(shù)： | 11/110頁(yè) |
| 文件大?。?/td> | 1737K |
| 代理商： | PSD834F3V-15 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)
11/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Reset
48
I
Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table
6
).
Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
burst mode.
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note:
PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table
6
).
Note:
PB0-PB3 can only output CMOS signals with an option for high slew rate.
However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
Input to the PLDs.
TMS Input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
Input to the PLDs.
TCK Input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
Pin Name
Pin
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD8532V20MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8532V70JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8532V70MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8532V70MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD8532V90MIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD835G2-70U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-12UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。