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參數(shù)資料
| 型號(hào)： | PSD835G1-70UI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲(chǔ)系統(tǒng) |
| 文件頁數(shù)： | 66/110頁 |
| 文件大?。?/td> | 570K |
| 代理商： | PSD835G1-70UI |
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PSD835G2
PSD8XX Family
65
The
PSD835G2
Functional
Blocks
(cont.)
Access
5V V
CC
,
Typical
Standby
Current
50 μA
(Note 2)
PLD
Memory
Access
Time
Recovery Time
to Normal
Access
Propagation
Delay
Normal tpd
(Note 1)
Mode
Power Down
No Access
tLVDV
Table 26. PSD835G2 Timing and Standby Current During Power
Down Mode
NOTES:
1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
Port Function
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
Pin Level
No Change
No Change
Undefined
Three-State
Three-State
Table 25. Power Down Mode’s Effect on
Ports
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.)
Power Down Mode
By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled.
The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive
for fifteen CLKIN (pin PD1) clock periods.
The following should be kept in mind when the PSD is in Power Down Mode:
If the address strobe starts pulsing again, the PSD will return to normal operation.
The PSD will also return to normal operation if either the CSI input returns low or the
Reset input returns high.
The MCU address/data bus is blocked from all memories and PLDs.
Various signals can be blocked (prior to Power Down Mode) from entering the PLDs
by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do
not
go into Standby Mode because you don’t want to
have to wait for the logic and I/O to “wake-up” before their outputs can change. See
Table 25 for Power Down Mode effects on PSD ports.
Typical standby current is 50 μA for 5 V parts. This standby current value assumes
that there are no transitions on any PLD input.
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| PSD835G1-90B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G1-90B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G1-90J | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G1-90JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD835G2-70U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2-90UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-12UI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| PSD835G2V-90U | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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