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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD835G1-C-90UI

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

    

    
文件頁(yè)數(shù)：
22/110頁(yè)

    

    
文件大?。?/td>
570K

    

    
代理商：
PSD835G1-C-90UI


    

    

    

	
    
    
    

    
    
	
    PSD835G2  
    PSD8XX Family
    21
    The 
    PSD835G2
    Functional
    Blocks
    (cont.)
    9.1.1.6.5   Data Polling Flag DQ7
    When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the 
    bit being entered for Programming/Writing on DQ7. Once the Program instruction or the
    Write operation is completed, the true logic value is read on DQ7 (in a Read operation).
    Flash memory specific features:
    J
     Data Polling is effective after the fourth Write pulse (for programming) or after the 
    sixth Write pulse (for Erase). It must be performed at the address being programmed 
    or at an address within the Flash sector being erased.
    J
     During an Erase instruction, DQ7 outputs a 
    ‘
    0
    ’
    .  After completion of the instruction, 
    DQ7 will output the last bit programmed (it is a 
    ‘
    1
    ’
     after erasing).
    J
     If the location to be programmed is in a protected Flash sector, the instruction is 
    ignored.
    J
     If all the Flash sectors to be erased are protected, DQ7 will be set to 
    ‘
    0
    ’
     for 
    about 100 μs, and then return to the previous addressed location. No erasure will be 
    performed.
    9.1.1.6.6   Toggle Flag DQ6
    The PSD835G2 offers another way for determining when the Flash memory Program 
    instruction is completed. During the internal Write operation and when either the FSi or
    CSBOOTi is true, the DQ6 will toggle from 
    ‘
    0
    ’
     to 
    ‘
    1
    ’
     and 
    ‘
    1
    ’
     to 
    ‘
    0
    ’
     on subsequent attempts to
    read any byte of the memory.
    When the internal cycle is complete, the toggling will stop and the data read on the 
    Data Bus D0-7 is the addressed memory location. The device is now accessible for a new 
    Read or Write operation. The operation is finished when two successive reads yield the
    same output data. Flash memory specific features:
    J
     The Toggle bit is effective after the fourth Write pulse (for programming) or after the 
    sixth Write pulse (for Erase).
    J
     If the location to be programmed belongs to a protected Flash sector, the instruction 
    is ignored.
    J
     If all the Flash sectors selected for erasure are protected, DQ6 will toggle to 
    ‘
    0
    ’
     for 
    about 100 μs and then return to the previous addressed location.
    9.1.1.6.7 Error Flag DQ5
    During a correct Program or Erase, the Error bit will set to 
    ‘
    0
    ’
    . This bit is set to 
    ‘
    1
    ’
     when 
    there is a failure during Flash programming, Sector erase, or Bulk Erase.
    In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
    bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
    The Error bit may also indicate a timeout condition while attempting to program a byte.
    In case of an error in Flash sector erase or byte program, the Flash sector in which the 
    error occurred or to which the programmed location belongs must no longer be used.
    Other Flash sectors may still be used. The Error bit resets after the Reset instruction.
    9.1.1.6.8 Erase Time-out Flag DQ3
    The Erase Timer bit reflects the time-out period allowed between two consecutive Sector 
    Erase instructions. The Erase timer bit is set to 
    ‘
    0
    ’
     after a Sector Erase instruction for a
    time period of 100 μs + 20% unless an additional Sector Erase instruction is decoded.
    After this time period or when the additional Sector Erase instruction is decoded, DQ3 is
    set to 
    ‘
    1
    ’
    .
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD835G1V-12B81
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G1V-12B81I
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G1V-A-70MI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G1V-A-70U
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G1V-A-70UI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD835G2-70U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2-90UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2V-12UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2V-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
    
    
    
	
    	
    
    
     
     
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