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    參數(shù)資料
    型號(hào): PSD8533V70MT
    廠商: 意法半導(dǎo)體
    英文描述: 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SO PowerPAD -40 to 140
    中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
    文件頁(yè)數(shù): 55/110頁(yè)
    文件大小: 1737K
    代理商: PSD8533V70MT
    55/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    Address In Mode
    For MCUs that have more than 16 address sig-
    nals, the higher addresses can be connected to
    Port A, B, C, and D. The address input can be
    latched in the Input Macrocell (IMC) by Address
    Strobe (ALE/AS, PD0). Any input that is included
    in the DPLD equations for the SRAM, or primary or
    secondary Flash memory is considered to be an
    address input.
    Data Port Mode
    Port A can be used as a data bus port for a MCU
    with a non-multiplexed address/data bus. The
    Data Port is connected to the data bus of the MCU.
    The general I/O functions are disabled in Port A if
    the port is configured as a Data Port.
    Peripheral I/O Mode
    Peripheral I/O mode can be used to interface with
    external peripherals. In this mode, all of Port A
    serves as a tri-state, bi-directional data buffer for
    the MCU. Peripheral I/O Mode is enabled by set-
    ting Bit 7 of the VM Register to a ’1.’ Figure
    27
    shows how Port A acts as a bi-directional buffer for
    the MCU data bus if Peripheral I/O Mode is en-
    abled. An equation for PSEL0 and/or PSEL1 must
    be written in PSDabel. The buffer is tri-stated
    when PSEL0 or PSEL1 is not active.
    Figure 27. Peripheral I/O Mode
    RD
    PSEL0
    PSEL1
    PSEL
    VM REGISTER BIT 7
    WR
    PA0-PA7
    D0-D7
    DATA BUS
    AI02886
    相關(guān)PDF資料
    PDF描述
    PSD8533V90MIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
    PSD8533V90MT 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SO PowerPAD -40 to 140
    PSD853412JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
    PSD853412JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
    PSD853412MIT 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SOIC -40 to 140
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD853F2-70J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
    PSD853F2-70M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100