參數資料
型號： PSD853420MT
廠商： 意法半導體
英文描述： 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SOIC -40 to 125
中文描述： Flash在系統(tǒng)可編程ISP的外設的8位微控制器
文件頁數： 16/110頁
文件大?。?/td> 1737K
代理商： PSD853420MT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
16/110
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table
4
indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the MCU. The primary Flash memory can
also be programmed in-system by the MCU exe-
cuting the programming algorithms out of the sec-
ondary memory, or SRAM. The secondary
memory can be programmed the same way by ex-
ecuting out of the primary Flash memory. The PLD
or other PSD Configuration blocks can be pro-
grammed through the JTAG port or a device pro-
grammer. Table
5
indicates which programming
methods can program different functional blocks
of the PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled
POWER MANAGEMENT, page 62
for
more details.
Table 4. JTAG SIgnals on Port C
Table 5. Methods of Programming Different Functional Blocks of the PSD
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Functional Block
JTAG Programming
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
相關PDF資料
PDF描述
PSD853470JIT 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SO PowerPAD -40 to 125
PSD853470JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD853470MIT 120V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 8-SO PowerPAD -40 to 125
PSD853470MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD853490JIT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
相關代理商/技術參數
參數描述
PSD853F2-70J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD853F2-70M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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