參數(shù)資料
型號(hào)： PSD854F2V-15M
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁(yè)數(shù)： 70/109頁(yè)
文件大?。?/td> 908K
代理商： PSD854F2V-15M
Obsolete
Product(s)
- Obsolete
Product(s)
63/109
PSD813F2V, PSD854F2V
Doc ID 10552 Rev 3
Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 32, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD enters Power-down mode, as discussed
next.
Power-down Mode. By default, if you enable the
APD Unit, Power-down mode is automatically en-
abled. The device enters Power-down mode if Ad-
dress Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
–
If Address Strobe (ALE/AS, PD0) starts
pulsing again, the PSD returns to normal
Operating mode. The PSD also returns to
normal Operating mode if either PSD Chip
Select Input (CSI, PD2) is Low or the Reset
(RESET) input is High.
–
The MCU address/data bus is blocked from all
memory and PLDs.
–
Various signals can be blocked (prior to
Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR
registers. The blocked signals include MCU
control signals and the common CLKIN (PD1).
Note that blocking CLKIN (PD1) from the
PLDs does not block CLKIN (PD1) from the
APD Unit.
–
All PSD memories enter standby mode and
are drawing standby current. However, the
PLD and I/O ports blocks do not go into
standby Mode because you don’t want to have
to wait for the logic and I/O to “wake-up”
before their outputs can change. See Table 28
for Power-down mode effects on PSD ports.
–
Typical standby current is of the order of
microamperes. These standby current values
assume that there are no transitions on any
PLD input.
Table 28. Power-down Mode’s Effect on Ports
Figure 32. APD Unit
Table 29. PSD Timing and Standby Current during Power-down Mode
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Tri-State
Peripheral I/O
Tri-State
Mode
PLD Propagation Delay
Memory
Access Time
Access Recovery Time
to Normal Access
Typical Standby Current
5V VCC
3V VCC
Power-down
Normal tPD (Note
1)
No Access
tLVDV
75A (Note 2)
25A (Note 2)
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
SELECT
AI02891
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