參數(shù)資料
型號: PSD9132V12JIT
廠商: 意法半導(dǎo)體
英文描述: IC LOGIC 244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS -40+85C SOIC-20 38/TUBE
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 61/110頁
文件大?。?/td> 1737K
代理商: PSD9132V12JIT
61/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
External Chip Select
The CPLD also provides three External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used to select external devices. Each External
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure
31
.)
Figure 31. Port D External Chip Select Signals
P
POLARITY
BIT
PD2 PIN
PT2
ECS2
DIRECTION
REGISTER
POLARITY
BIT
PD1 PIN
PT1
ECS1
ENABLE (.OE)
ENABLE (.OE)
DIRECTION
REGISTER
POLARITY
BIT
PD0 PIN
PT0
ECS0
ENABLE (.OE)
DIRECTION
REGISTER
C
AI02890
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