參數(shù)資料
型號(hào): PSD913390JT
廠商: 意法半導(dǎo)體
英文描述: Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 50/110頁
文件大小: 1737K
代理商: PSD913390JT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
50/110
68HC11
Figure
25
shows a bus interface to a 68HC11
where the PSD is configured in 8-bit multiplexed
mode with E and R/W settings. The DPLD can be
used to generate the READ and WR signals for
external devices.
Figure 25. Interfacing the PSD with a 68HC11
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(R_W)
CNTL1(E)
CNTL2
PD0–AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A14
A15
A13
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
31
30
29
28
27
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
PSD
RESET
RESET
AD7-AD0
AD7-AD0
AI02884C
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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