參數(shù)資料
型號: PSD9133V15MT
廠商: 意法半導(dǎo)體
英文描述: Quad TTL-ECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 48/110頁
文件大?。?/td> 1737K
代理商: PSD9133V15MT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
48/110
Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
Table 18. 80C251 Configurations
Configuration
80C251 READ/WRITE
Pins
Connecting to PSD Pins
Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31 compatible A7-
A0 multiplex with D7-D0
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A7-A0 multiplex with D7-D0
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A15-A8 multiplex with D7-D0
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
27
28
29
30
31
43
42
41
40
39
38
37
36
24
25
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD14
AD15
AD13
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD15
ALE
RD
WR
PSEN
AD14
14
15
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
X2
X1
RST
EA
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.0
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB
PSD
RESET
RESET
35
16
17
10
RESET
AI02882C
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